Hochoptimierte Open-Source-RISC-V-Prozessoren für universelle Anwendungen

To save time in the development of modern Systems-on-Chip (SoCs) and reduce development complexity, it is essential to use IP components, which are available as both proprietary and open-source modules. Programmable soft-core processors are particularly relevant, as they are used as control units in SoCs and are also available as open source. Despite the advantages of open cores, such as a modifiable and extensible hardware description, the drawbacks of many hardware projects from various sources are significant. In many cases, there is only a so-called behavioral hardware description, which is not always optimally mapped for different target platforms (ASIC, FPGA) and design requirements.

This project aims to address these weaknesses by developing a highly optimized and configurable soft-core processor family based on the RISC-V open-source architecture. Compiler support will be added by extending the architecture targets of the existing LLVM backend. An aligned open-source synthesis toolflow will generate optimized netlists. The resulting open-source framework will be published. For demonstration purposes, various example applications will be implemented and deployed on the Cologne Chip GateMate FPGA as part of the project.